1. Field of the Invention
The invention relates to a dynamic random access memory and in particular to an electrostatic discharge structure of a dynamic random access memory.
2. Description of the Related Art
For a dynamic random access memory (hereinafter referred to as DRAM), the data storage status is determined by charging or discharging of the array of capacitors on the semiconductor substrate. In general, charging status of a capacitor is represented as “1”, and discharging status of a capacitor is represented as “0”. If operating voltage and upper/lower electrode plate dielectric constant is fixed, the amount of storage charges is determined by the surface area of the capacitors in DRAM.
Ordinarily, a DRAM has an electrostatic discharge (hereinafter referred to as ESD) region between a periphery region and a device region. The ESD region prevents electrostatic charges from interrupting operations or damaging the DRAM. In general, higher ESD resistance results in less current produced by electrostatic discharge, such that the circuit is protected from large instantaneous electrostatic charges. Reducing the contact area between the plug and the substrate to increase electrostatic resistance without enhancing the plug aspect ratio, and simultaneously improving the mechanism strength of the ESD region are major objectives in the field.